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Hexagon (QDSP6) is a digital signal processor (DSP), based 32-bit multithreaded architecture developed by Qualcomm. According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its SoCs (average 2.3 DSP core per SoC) in 2011 year, and 1.5 billion cores were planned for 2012, making the QDSP most shipped architecture of DSP〔Will Strauss, (Forward Concepts. Wireless/DSP Market Bulletin: Qualcomm Leads in Global DSP Silicon Shipments ) // Forward Concepts: "In calendar year 2011, Qualcomm shipped a reported 521 million MSM chip shipments and we estimate that an average of 2.3 of its DSP cores in each unit resulted in 1.2 billion DSPs shipped in silicon. This (calendar) year, we estimate that the company will ship an average of 2.4 DSP cores with each (more complex) MSM chip."〕 (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market〔(); (); (Ceva grabs 90% of DSP IP market ), 2012〕). The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, VLIW, SIMD,〔Hexagon v2 Programmers Reference〕 and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.〔(Porting LLVM to a Next Generation DSP ), L. Taylor Simpson (Qualcomm) // LLVM Developers’ Meeting: 11/18/2011〕 Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so 600 MHz physical core is presented as three logical 200 MHz cores before V5.〔(Faster 128-EEA3 and 128-EIA3 Software ), Roberto Avanzi and Billy Bob Brumley (Qualcomm Research), Cryptology ePrint Archive: Report 2013/428, 2 Jul 2013. Page 9.〕〔 Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.〔〔(Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading ) // Linley Gwennap, Microprocessor Report, August 2013〕 The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"〔https://developer.qualcomm.com/download/80-nb419-3ahexagonvirtualmachinespec.pdf (restricted access)〕) and was merged with the 3.2 release of the kernel.〔(【引用サイトリンク】title=3.2 merge window, part 1 )〕〔(Linux Kernel 3.2 Release Notes ) "1.4. New architecture: Hexagon"〕 The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.〔Richard Kuo, (Hexagon MiniVM ) // linux.ports.hexagon, 25 Apr 2013〕〔(Hexagon MiniVM ) // CodeAurora (Qualcomm)〕 Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum. There is also a non-FSF maintained branch of GCC and binutils.〔(【引用サイトリンク】url=https://www.codeaurora.org/xwiki/bin/Hexagon/ ) 〕 Hexagon DSPs are included in Snapdragon SoC since 2006.〔(Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4 ), 10/12/2011 by John Oram. Quote: "Hexagon DSPs have been in Snapdragon chips since 2006."〕〔(QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core ) // InsideDSP, June 22, 2012〕 In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user. They are also used in some femtocell processors of Qualcomm, including FSM9832.〔(Qualcomm Aims Hexagon at Femtocells ), October 31, 2011. Linley Gwennap// Linley WIRE〕 == Versions == There are four versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011); and QDSP6 V5 (2013, in Snapdragon 800〔(Qualcomm Announces Next Generation Snapdragon Premium Mobile Processors )// Qualcomm, January 07, 2013〕).〔 V4 has 20 DMIPS per milliwatt, operating at 500 MHz.〔〔 Clock speed of Hexagon varies in 400–600 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.〔(【引用サイトリンク】title=List of Snapdragon SoCs )〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Qualcomm Hexagon」の詳細全文を読む スポンサード リンク
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